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fuchsia.hardware.pciroot

PROTOCOLS

Pciroot

Defined in fuchsia.hardware.pciroot/pciroot.fidl

AllocateMsi

Allocate |msi_count| MSIs and return a handle to the backing MsiAllocation.

Request

NameType
msi_count uint32
can_target_64bit bool

Response

NameType
s zx/status
allocation handle<msi>

ConfigRead16

Read 16 bytes from config space for device at bdf address |address|, offset |offset|.

Request

NameType
address PciBdf
offset uint16

Response

NameType
s zx/status
value uint16

ConfigRead32

Read 32 bytes from config space for device at bdf address |address|, offset |offset|.

Request

NameType
address PciBdf
offset uint16

Response

NameType
s zx/status
value uint32

ConfigRead8

Read 8 bytes from config space for device at bdf address |address|:we, offset |offset|.

Request

NameType
address PciBdf
offset uint16

Response

NameType
s zx/status
value uint8

ConfigWrite16

Write 16 bytes to config space for device at bdf |address| offset |offset|.

Request

NameType
address PciBdf
offset uint16
value uint16

Response

NameType
s zx/status

ConfigWrite32

Write 32 bytes to config space for device at bdf |address| offset |offset|.

Request

NameType
address PciBdf
offset uint16
value uint32

Response

NameType
s zx/status

ConfigWrite8

Write 8 bytes to config space for device at bdf |address| offset |offset|.

Request

NameType
address PciBdf
offset uint16
value uint8

Response

NameType
s zx/status

ConnectSysmem

Legacy methods Create a sysmem connection - used to implement fuchsia.hardware.sysmem.

Request

NameType
connection handle<channel>

Response

NameType
s zx/status

DriverShouldProxyConfig

Contemporary methods: Returns true if the bus driver should proxy all device config access to pciroot. This is necessary in cases of IO config on x86, or for controllers that require configuration to map in device config headers.

Request

NameType

Response

NameType
use_proxy bool

GetAddressSpace

Request address space reservations from platform bus to use for mapping bars / bridges |in_base| is an optional requested start address which should otherwise be 0. |size| is the size of the request in bytes. |low| dictates whether the allocation should be an address below 4 GB or not.

On success, the base address is provided in |out_base| and the size is |size|.

An error will be returned if |size| cannot be fulfilled, |low| is set with |in_base|+|size| being >=4GB, or if a requested |in_base| cannot be provided.

Request

NameType
in_base zx/paddr
size uint64
type PciAddressSpace
low bool

Response

NameType
s zx/status
base zx/paddr
resource handle<resource>
token handle<eventpair>

GetBti

Request

NameType
bdf uint32
index uint32

Response

NameType
s zx/status
bti handle<bti>

GetPciPlatformInfo

Get the platform information structure from the pciroot protocol to be used for bus init.

Request

NameType

Response

NameType
s zx/status
info PciPlatformInfo

STRUCTS

PciBdf

Defined in fuchsia.hardware.pciroot/pciroot.fidl

NameTypeDescriptionDefault
bus_id uint8 No default
device_id uint8 No default
function_id uint8 No default

PciIrqRoutingEntry

Defined in fuchsia.hardware.pciroot/pciroot.fidl

A protocol representation of a routing entry. It is intentionally very similar to an ACPI _PRT entry to reduce the complexity of the data structure that needs to be passed over the 'wire'. Endpoints directly connected to a root complex will have port device and function_ids of PCI_IRQ_ROUTING_NO_PARENT. For other endpoints hanging off root ports or bridges their upstream port address will be contained in these fields.

NameTypeDescriptionDefault
port_device_id uint8 No default
port_function_id uint8 No default
device_id uint8 No default
pins uint8[4] No default

PciLegacyIrq

Defined in fuchsia.hardware.pciroot/pciroot.fidl

This represents one of the vectors wired up for PCI legacy interrupts. How the bus driver uses them depends on the irq routing table provided to them. The vector is supplied because interrupt objects cannot be inspected with zx_get_object_info.

NameTypeDescriptionDefault
interrupt handle<interrupt> No default
vector uint32 No default

PciPlatformInfo

Defined in fuchsia.hardware.pciroot/pciroot.fidl

This structure is the primary means of passing PCI platform information from the platform bus implementation to the PCI bus driver. If an ecam is found for this segment group then a handle to a VMO for it will be provided via |ecam_vmo|. The VMO's start address will correspond to the base address of the bus number specified by |start_bus_num|.

NameTypeDescriptionDefault
name string[8] No default
start_bus_num uint8 No default
end_bus_num uint8 No default
segment_group uint16 No default
ecam_vmo handle<vmo> No default
legacy_irqs vector<PciLegacyIrq> No default
irq_routing vector<PciIrqRoutingEntry> No default

ENUMS

PciAddressSpace

Type: uint8

Defined in fuchsia.hardware.pciroot/pciroot.fidl

NameValueDescription
MEMORY 0
IO 1

CONSTANTS

NameValueTypeDescription
DEVICES_PER_BUS 64 uint8
FUNCTIONS_PER_DEVICE 8 uint8
PCI_IRQ_ROUTING_ALL_FUNCTIONS 15 uint8

An entry corresponds to all functions for the given device.

PCI_IRQ_ROUTING_NO_PARENT 255 uint8

Used to indicate within a routing entry that there is no parent bridge/port device, it is connected directly at the root.

PINS_PER_FUNCTION 4 uint8