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fuchsia.hardware.sdhci

PROTOCOLS

Sdhci

Defined in fuchsia.hardware.sdhci/sdhci.fidl

GetBaseClock

Request

<EMPTY>

Response

NameType
clock uint32

GetBti

Gets a handle to the bus transaction initiator for the device. The caller receives ownership of the handle.

Request

NameType
index uint32

Response

NameType
s zx/status
bti handle<bti>

GetInterrupt

Request

<EMPTY>

Response

NameType
s zx/status
irq handle<interrupt>

GetMmio

mmio size minus offset must be at least 512 bytes as per the SDHCI specification.

Request

<EMPTY>

Response

NameType
s zx/status
mmio handle<vmo>
offset zx/off

GetQuirks

returns device quirks

Request

<EMPTY>

Response

NameType
quirks uint64
dma_boundary_alignment uint64

HwReset

platform specific HW reset

Request

<EMPTY>

Response

<EMPTY>

STRUCTS

ENUMS

SdhciQuirk strict

Type: uint64

Defined in fuchsia.hardware.sdhci/sdhci.fidl

NameValueDescription
STRIP_RESPONSE_CRC 1

This is a BCM28xx specific quirk. The bottom 8 bits of the 136 bit response are normally filled by 7 CRC bits and 1 reserved bit. The BCM controller checks the CRC for us and strips it off in the process. The higher level stack expects 136B responses to be packed in a certain way so we shift all the fields back to their proper offsets.

NO_DMA 2

BCM28xx quirk: The BCM28xx appears to use its internal DMA engine to perform transfers against the SD card. Normally we would use SDMA or ADMA (if the part supported it). Since this part doesn't appear to support either, we just use PIO.

STRIP_RESPONSE_CRC_PRESERVE_ORDER 4

The bottom 8 bits of the 136 bit response are normally filled by 7 CRC bits and 1 reserved bit. Some controllers strip off the CRC. The higher level stack expects 136B responses to be packed in a certain way so we shift all the fields back to their proper offsets.

NON_STANDARD_TUNING 8

The controller uses a tuning process that does not follow the SDHCI specification.

NO_DDR 16

Don't use DDR modes even if the SDHCI capabilites register indicates it is supported.

USE_DMA_BOUNDARY_ALIGNMENT 32

Prevent DMA buffers from crossing boundaries specified by dma_boundary_alignment. For example, a boundary alignment of 0x10000 will cause buffers crossing 64K boundaries to be split across multiple descriptors.