zx_riscv64_thread_state_general_regs_t
Summary
Public attributes
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a0
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uint64_t
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a1
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uint64_t
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a2
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uint64_t
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a3
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uint64_t
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a4
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uint64_t
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a5
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uint64_t
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a6
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uint64_t
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a7
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uint64_t
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gp
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uint64_t
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pc
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uint64_t
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ra
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uint64_t
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s0
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uint64_t
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s1
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uint64_t
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s10
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uint64_t
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s11
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uint64_t
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s2
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uint64_t
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s3
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uint64_t
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s4
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uint64_t
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s5
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uint64_t
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s6
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uint64_t
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s7
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uint64_t
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s8
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uint64_t
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s9
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uint64_t
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sp
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uint64_t
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t0
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uint64_t
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t1
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uint64_t
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t2
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uint64_t
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t3
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uint64_t
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t4
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uint64_t
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t5
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uint64_t
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t6
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uint64_t
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tp
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uint64_t
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Public attributes
a0
uint64_t zx_riscv64_thread_state_general_regs_t::a0
a1
uint64_t zx_riscv64_thread_state_general_regs_t::a1
a2
uint64_t zx_riscv64_thread_state_general_regs_t::a2
a3
uint64_t zx_riscv64_thread_state_general_regs_t::a3
a4
uint64_t zx_riscv64_thread_state_general_regs_t::a4
a5
uint64_t zx_riscv64_thread_state_general_regs_t::a5
a6
uint64_t zx_riscv64_thread_state_general_regs_t::a6
a7
uint64_t zx_riscv64_thread_state_general_regs_t::a7
gp
uint64_t zx_riscv64_thread_state_general_regs_t::gp
pc
uint64_t zx_riscv64_thread_state_general_regs_t::pc
ra
uint64_t zx_riscv64_thread_state_general_regs_t::ra
s0
uint64_t zx_riscv64_thread_state_general_regs_t::s0
s1
uint64_t zx_riscv64_thread_state_general_regs_t::s1
s10
uint64_t zx_riscv64_thread_state_general_regs_t::s10
s11
uint64_t zx_riscv64_thread_state_general_regs_t::s11
s2
uint64_t zx_riscv64_thread_state_general_regs_t::s2
s3
uint64_t zx_riscv64_thread_state_general_regs_t::s3
s4
uint64_t zx_riscv64_thread_state_general_regs_t::s4
s5
uint64_t zx_riscv64_thread_state_general_regs_t::s5
s6
uint64_t zx_riscv64_thread_state_general_regs_t::s6
s7
uint64_t zx_riscv64_thread_state_general_regs_t::s7
s8
uint64_t zx_riscv64_thread_state_general_regs_t::s8
s9
uint64_t zx_riscv64_thread_state_general_regs_t::s9
sp
uint64_t zx_riscv64_thread_state_general_regs_t::sp
t0
uint64_t zx_riscv64_thread_state_general_regs_t::t0
t1
uint64_t zx_riscv64_thread_state_general_regs_t::t1
t2
uint64_t zx_riscv64_thread_state_general_regs_t::t2
t3
uint64_t zx_riscv64_thread_state_general_regs_t::t3
t4
uint64_t zx_riscv64_thread_state_general_regs_t::t4
t5
uint64_t zx_riscv64_thread_state_general_regs_t::t5
t6
uint64_t zx_riscv64_thread_state_general_regs_t::t6
tp
uint64_t zx_riscv64_thread_state_general_regs_t::tp
