zx_riscv64_thread_state_general_regs_t

Summary

Public attributes

a0
uint64_t
a1
uint64_t
a2
uint64_t
a3
uint64_t
a4
uint64_t
a5
uint64_t
a6
uint64_t
a7
uint64_t
gp
uint64_t
pc
uint64_t
ra
uint64_t
s0
uint64_t
s1
uint64_t
s10
uint64_t
s11
uint64_t
s2
uint64_t
s3
uint64_t
s4
uint64_t
s5
uint64_t
s6
uint64_t
s7
uint64_t
s8
uint64_t
s9
uint64_t
sp
uint64_t
t0
uint64_t
t1
uint64_t
t2
uint64_t
t3
uint64_t
t4
uint64_t
t5
uint64_t
t6
uint64_t
tp
uint64_t

Public attributes

a0

uint64_t zx_riscv64_thread_state_general_regs_t::a0

a1

uint64_t zx_riscv64_thread_state_general_regs_t::a1

a2

uint64_t zx_riscv64_thread_state_general_regs_t::a2

a3

uint64_t zx_riscv64_thread_state_general_regs_t::a3

a4

uint64_t zx_riscv64_thread_state_general_regs_t::a4

a5

uint64_t zx_riscv64_thread_state_general_regs_t::a5

a6

uint64_t zx_riscv64_thread_state_general_regs_t::a6

a7

uint64_t zx_riscv64_thread_state_general_regs_t::a7

gp

uint64_t zx_riscv64_thread_state_general_regs_t::gp

pc

uint64_t zx_riscv64_thread_state_general_regs_t::pc

ra

uint64_t zx_riscv64_thread_state_general_regs_t::ra

s0

uint64_t zx_riscv64_thread_state_general_regs_t::s0

s1

uint64_t zx_riscv64_thread_state_general_regs_t::s1

s10

uint64_t zx_riscv64_thread_state_general_regs_t::s10

s11

uint64_t zx_riscv64_thread_state_general_regs_t::s11

s2

uint64_t zx_riscv64_thread_state_general_regs_t::s2

s3

uint64_t zx_riscv64_thread_state_general_regs_t::s3

s4

uint64_t zx_riscv64_thread_state_general_regs_t::s4

s5

uint64_t zx_riscv64_thread_state_general_regs_t::s5

s6

uint64_t zx_riscv64_thread_state_general_regs_t::s6

s7

uint64_t zx_riscv64_thread_state_general_regs_t::s7

s8

uint64_t zx_riscv64_thread_state_general_regs_t::s8

s9

uint64_t zx_riscv64_thread_state_general_regs_t::s9

sp

uint64_t zx_riscv64_thread_state_general_regs_t::sp

t0

uint64_t zx_riscv64_thread_state_general_regs_t::t0

t1

uint64_t zx_riscv64_thread_state_general_regs_t::t1

t2

uint64_t zx_riscv64_thread_state_general_regs_t::t2

t3

uint64_t zx_riscv64_thread_state_general_regs_t::t3

t4

uint64_t zx_riscv64_thread_state_general_regs_t::t4

t5

uint64_t zx_riscv64_thread_state_general_regs_t::t5

t6

uint64_t zx_riscv64_thread_state_general_regs_t::t6

tp

uint64_t zx_riscv64_thread_state_general_regs_t::tp