Hardware requirements and recommendations

This page is a summary of Fuchsia's current hardware requirements and recommendations. The goal is to provide an easy to understand explanation of RFC-0111: Initial hardware platform specifications for hardware vendors who only need to know what hardware features Fuchsia requires or recommends.

Required features

All required features must be supported. If a required feature is not supported, Fuchsia will not build or run correctly.

Feature Area Details Examples
Instruction set architecture (ISA) Architecture
  • x86-64 architectures must support x86-64-v2 ISA.
  • Arm architectures must support Armv8.0-A at minimum.
  • Intel Westmere and newer CPUs.
  • AMD Bulldozer and newer CPUs.
  • Arm A35, A53, A55, A57, A65, A72, A73, A75, A76, A77, A78, and X1.
QEMU support Architecture
Little endian byte-ordering mode Architecture
  • All x86 CPUs.
  • Arm processors support little endian.
LLVM toolchain support Architecture
  • The architecture must be in the LLVM core tier.
  • Clang toolchain support must be kept up-to-date.
Tier 2 Rust language support Architecture
Dart language support Architecture
Go language support Architecture
Full-featured modern memory management unit (MMU) Platform
  • The MMU must support creating an arbitrary number of address spaces.
  • The MMU must map physical memory in reasonably sized pages to any of those spaces.
  • The MMU must enforce protection between separate address spaces through hardware access control mechanisms.
  • Armv8.0-A and later.
  • All x86 CPUs after 2010.
64-bit platform Platform
  • The platform must support 64-bit address space operating mode.
  • The early stage bootloader doesn't need to run in 64-bit mode.
  • All x86-64 platforms.
  • All Armv8-A and later processors (except A32).
Clocks and timers System
  • Clocks and timers must not arbitrarily change frequency.
  • Clocks and timers must be at least 56-bits wide.
  • Clocks and timers must have a rollover time greater than 40 years.
  • Clocks and timers must have an explicitly knowable nominal frequency that doesn't require runtime calibration.
Bootloader openness System
Serial console access System
  • The system must support interrupt-driven TX and RX during development.
  • Serial console access is not required for production systems intended for end users.
  • (Recommended) Direct memory access (DMA).

Recommended features

Recommended features are not required to build or run Fuchsia correctly but are highly desirable because they improve Fuchsia's base functionality.

Feature Area Details Examples
Virtualization support Architecture
  • Intel x86 CPUs: VMX, EPT, RDTSCP, x2APIC, VPID, unrestricted guests, TPR virtualization, MSR bitmaps, exception bitmaps, INVPCID (recommended), PAUSE-loop exiting (recommended).
  • Arm CPUs: Armv8.0, EL2 access, host physical timer / guest virtual timer split, GICv2 or GICv3, GIC virtualization.
  • Armv8-A AArch64.
  • Intel VT-x.
  • AMD VT.
Clocks and timers Architecture
  • Timers should deliver interrupts to cores when timer values exceed a given absolute threshold.
  • Clocks and timers should be implemented as part of the architecture itself, not as a peripheral.
I/O memory management unit (IOMMU) Platform
  • The IOMMU should be able to NAK read and write transactions initiated from uniquely identifiable hardware units.
  • The IOMMU should do address translation for hardware DMA operations.
  • IOMMU page-fault situations should be detectable and debuggable.
  • System Memory Management Unit (SMMU) in Arm IOMMU spec.
  • Intel x86 IOMMU spec.
  • Intel VT-d.
  • AMD-Vi.
Hardware cryptographic acceleration support Platform
  • The platform should provide hardware acceleration for AES and SHA.
  • AES for Armv8.0-A (Cortex A34) or later: AESE, AESD, AESMC, AESIMC, PMULL, PMULL2.
  • SHA2 for Armv8.0-A (Cortex A34) or later: SHA256H, SHA256H2, SHA256UO, SHA256U1.
Hardware-assisted tracing Platform
  • Arm CoreSight ETM.
  • Intel Last Branch Records (LBR).
GCC toolchain support System
  • The system should be fully supported by the GCC toolchain.
Tier 1 Rust language support System
Documentation and support System
  • The system should have publicly available documentation about register maps, theory of operation, and boot-time hardware state.
  • Board documentation can't be a fork of the documentation source code for Linux or Android Open Source Project or any other project that has a license incompatible with Fuchsia.
  • The system vendor must provide support channels where Fuchsia contributors can get their questions answered.
Fastboot support System
  • The bootloader should support fastboot over non-proprietary transports. See Required fastboot commands for the full list of fastboot protocol commands that should be supported.

Appendix: Terminology

These terminology definitions are based on Document Definitions.


A processor architecture like x86 or Arm.

Early stage bootloader

All stages of the bootloader before the final-stage bootloader.

Final-stage bootloader

The software component that loads Fuchsia's kernel.


The system-on-a-chip (SoC) or the combination of the CPU and chipset.


A complete computer hardware system with a CPU, memory, peripherals and so on. Also called a board.