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fuchsia.hardware.pci

PROTOCOLS

Bus

Defined in fuchsia.hardware.pci/pci.fidl

GetDevices

Request

NameType

Response

NameType
devices vector<Device>[64]

GetHostBridgeInfo

Request

NameType

Response

NameType
info HostBridgeInfo

Pci

Defined in fuchsia.hardware.pci/pci.fidl

fxbug.dev/33713: Remove the zx_pcie types and implement them here

AckInterrupt

Request

NameType

Response

NameType
s zx/status

ConfigRead16

Request

NameType
offset uint16

Response

NameType
s zx/status
value uint16

ConfigRead32

Request

NameType
offset uint16

Response

NameType
s zx/status
value uint32

ConfigRead8

Request

NameType
offset uint16

Response

NameType
s zx/status
value uint8

ConfigWrite16

Request

NameType
offset uint16
value uint16

Response

NameType
s zx/status

ConfigWrite32

Request

NameType
offset uint16
value uint32

Response

NameType
s zx/status

ConfigWrite8

Request

NameType
offset uint16
value uint8

Response

NameType
s zx/status

ConfigureIrqMode

Request

NameType
requested_irq_count uint32

Response

NameType
s zx/status
mode PciIrqMode

EnableBusMaster

Request

NameType
enable bool

Response

NameType
s zx/status

GetBar

Request

NameType
bar_id uint32

Response

NameType
s zx/status
res fuchsia.hardware.syscalls.pci/PciBar

GetBti

Request

NameType
index uint32

Response

NameType
s zx/status
bti handle<bti>

GetDeviceInfo

Request

NameType

Response

NameType
s zx/status
info fuchsia.hardware.syscalls.pci/PcieDeviceInfo

GetFirstCapability

Request

NameType
id uint8

Response

NameType
s zx/status
offset uint8

GetFirstExtendedCapability

Request

NameType
id uint16

Response

NameType
s zx/status
offset uint16

GetNextCapability

Request

NameType
id uint8
offset uint8

Response

NameType
s zx/status
offset uint8

GetNextExtendedCapability

Request

NameType
id uint16
offset uint16

Response

NameType
s zx/status
offset uint16

MapInterrupt

Request

NameType
which_irq uint32

Response

NameType
s zx/status
handle handle<interrupt>

QueryIrqMode

Request

NameType
mode fuchsia.hardware.syscalls.pci/PciIrqMode

Response

NameType
s zx/status
max_irqs uint32

ResetDevice

Request

NameType

Response

NameType
s zx/status

SetIrqMode

Request

NameType
mode fuchsia.hardware.syscalls.pci/PciIrqMode
requested_irq_count uint32

Response

NameType
s zx/status

STRUCTS

BaseAddress

Defined in fuchsia.hardware.pci/pci.fidl

NameTypeDescriptionDefault
address uint64 No default
size uint64 No default
is_memory bool No default
is_prefetchable bool No default
is_64bit bool No default
id uint8 No default

Capability

Defined in fuchsia.hardware.pci/pci.fidl

NameTypeDescriptionDefault
id uint8 No default
offset uint8 No default

Device

Defined in fuchsia.hardware.pci/pci.fidl

NameTypeDescriptionDefault
base_addresses vector<BaseAddress>[6] No default
capabilities vector<Capability>[32] No default
ext_capabilities vector<ExtendedCapability>[32] No default
config vector<uint8>[256] No default
bus_id uint8 No default
device_id uint8 No default
function_id uint8 No default

ExtendedCapability

Defined in fuchsia.hardware.pci/pci.fidl

NameTypeDescriptionDefault
id uint16 No default
offset uint16 No default

HostBridgeInfo

Defined in fuchsia.hardware.pci/pci.fidl

NameTypeDescriptionDefault
start_bus_number uint8 No default
end_bus_number uint8 No default
segment_group uint16 No default

ENUMS

PciCapId strict

Type: uint8

Defined in fuchsia.hardware.pci/pci.fidl

NameValueDescription
NULL 0
PCI_PWR_MGMT 1
AGP 2
VITAL_PRODUCT_DATA 3
SLOT_IDENTIFICATION 4
MSI 5
COMPACT_PCI_HOTSWAP 6
PCIX 7
HYPERTRANSPORT 8
VENDOR 9
DEBUG_PORT 10
COMPACT_PCI_CRC 11
PCI_HOT_PLUG 12
PCI_BRIDGE_SUBSYSTEM_VID 13
AGP8X 14
SECURE_DEVICE 15
PCI_EXPRESS 16
MSIX 17
SATA_DATA_NDX_CFG 18
ADVANCED_FEATURES 19
ENHANCED_ALLOCATION 20
FLATTENING_PORTAL_BRIDGE 21

PciCfg strict

Type: uint16

Defined in fuchsia.hardware.pci/pci.fidl

NameValueDescription
VENDOR_ID 0
DEVICE_ID 2
COMMAND 4
STATUS 6
REVISION_ID 8
CLASS_CODE_INTR 9
CLASS_CODE_SUB 10
CLASS_CODE_BASE 11
CACHE_LINE_SIZE 12
LATENCY_TIMER 13
HEADER_TYPE 14
BIST 15
BASE_ADDRESSES 16
CARDBUS_CIS_PTR 40
SUBSYSTEM_VENDOR_ID 44
SUBSYSTEM_ID 46
EXP_ROM_ADDRESS 48
CAPABILITIES_PTR 52
INTERRUPT_LINE 60
INTERRUPT_PIN 61
MIN_GRANT 62
MAX_LATENCY 63

PciExtCapId strict

Type: uint16

Defined in fuchsia.hardware.pci/pci.fidl

NameValueDescription
NULL 0
ADVANCED_ERROR_REPORTING 1
VIRTUAL_CHANNEL_NO_MFVC 2
DEVICE_SERIAL_NUMBER 3
POWER_BUDGETING 4
ROOT_COMPLEX_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION 7
MULTI_FUNCTION_VIRTUAL_CHANNEL 8
VIRTUAL_CHANNEL 9
RCRB 10
VENDOR 11
CAC 12
ACS 13
ARI 14
ATS 15
SR_IOV 16
MR_IOV 17
MULTICAST 18
PRI 19
ENHANCED_ALLOCATION 20
RESIZABLE_BAR 21
DYNAMIC_POWER_ALLOCATION 22
TPH 23
LATENCY_TOLERANCE_REPORTING 24
SECONDARY_PCI_EXPRESS 25
PMUX 26
PASID 27
LNR 28
DPC 29
L1PM_SUBSTATES 30
PRECISION_TIME_MEASUREMENT 31
MPCIE 32
FRS_QUEUEING 33
READINESS_TIME_REPORTING 34
DESIGNATED_VENDOR 35
VF_RESIZABLE_BAR 36
PHYSICAL_LAYER_16 38
LANE_MARGINING_AT_RECEIVER 39
HIERARCHY_ID 40
NATIVE_PCIE_ENCLOSURE 41
PHYSICAL_LAYER_32 42
ALTERNATE_PROTOCOL 43
SYSTEM_FIRMWARE_INTERMEDIARY 44

PciIrqMode strict

Type: uint8

Defined in fuchsia.hardware.pci/pci.fidl

NameValueDescription
DISABLED 0
LEGACY 1
LEGACY_NOACK 2
MSI 3
MSI_X 4
COUNT 5

CONSTANTS

NameValueTypeDescription
BASE_ADDRESS_COUNT 6 uint32
BASE_CONFIG_SIZE 256 uint32
MAX_CAPABILITIES 32 uint32
MAX_DEVICES 64 uint32
MAX_EXT_CAPABILITIES 32 uint32