PROTOCOLS
Bus
Defined in fuchsia.hardware.pci/pci.fidl
GetDevices
Request
| Name | Type |
|---|
Response
| Name | Type |
|---|---|
devices |
vector<Device>[64]
|
GetHostBridgeInfo
Request
| Name | Type |
|---|
Response
| Name | Type |
|---|---|
info |
HostBridgeInfo
|
STRUCTS
BaseAddress
Defined in fuchsia.hardware.pci/pci.fidl
| Name | Type | Description | Default |
|---|---|---|---|
address |
uint64
|
No default | |
size |
uint64
|
No default | |
is_memory |
bool
|
No default | |
is_prefetchable |
bool
|
No default | |
is_64bit |
bool
|
No default | |
id |
uint8
|
No default |
Capability
Defined in fuchsia.hardware.pci/pci.fidl
| Name | Type | Description | Default |
|---|---|---|---|
id |
uint8
|
No default | |
offset |
uint8
|
No default |
Device
Defined in fuchsia.hardware.pci/pci.fidl
| Name | Type | Description | Default |
|---|---|---|---|
base_addresses |
vector<BaseAddress>[6]
|
No default | |
capabilities |
vector<Capability>[32]
|
No default | |
ext_capabilities |
vector<ExtendedCapability>[32]
|
No default | |
config |
vector<uint8>[256]
|
No default | |
bus_id |
uint8
|
No default | |
device_id |
uint8
|
No default | |
function_id |
uint8
|
No default |
ExtendedCapability
Defined in fuchsia.hardware.pci/pci.fidl
| Name | Type | Description | Default |
|---|---|---|---|
id |
uint16
|
No default | |
offset |
uint16
|
No default |
HostBridgeInfo
Defined in fuchsia.hardware.pci/pci.fidl
| Name | Type | Description | Default |
|---|---|---|---|
start_bus_number |
uint8
|
No default | |
end_bus_number |
uint8
|
No default | |
segment_group |
uint16
|
No default |
CONSTANTS
| Name | Value | Type | Description |
|---|---|---|---|
| BASE_ADDRESS_COUNT |
6
|
uint32 |
|
| BASE_CONFIG_SIZE |
256
|
uint32 |
|
| MAX_CAPABILITIES |
32
|
uint32 |
|
| MAX_DEVICES |
64
|
uint32 |
|
| MAX_EXT_CAPABILITIES |
32
|
uint32 |