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fuchsia.hardware.pci

PROTOCOLS

Bus

Defined in fuchsia.hardware.pci/pci.fidl

GetDevices

Request

NameType

Response

NameType
devices vector<Device>[64]

GetHostBridgeInfo

Request

NameType

Response

NameType
info HostBridgeInfo

STRUCTS

BaseAddress

Defined in fuchsia.hardware.pci/pci.fidl

NameTypeDescriptionDefault
address uint64 No default
size uint64 No default
is_memory bool No default
is_prefetchable bool No default
is_64bit bool No default
id uint8 No default

Capability

Defined in fuchsia.hardware.pci/pci.fidl

NameTypeDescriptionDefault
id uint8 No default
offset uint8 No default

Device

Defined in fuchsia.hardware.pci/pci.fidl

NameTypeDescriptionDefault
base_addresses vector<BaseAddress>[6] No default
capabilities vector<Capability>[32] No default
ext_capabilities vector<ExtendedCapability>[32] No default
config vector<uint8>[256] No default
bus_id uint8 No default
device_id uint8 No default
function_id uint8 No default

ExtendedCapability

Defined in fuchsia.hardware.pci/pci.fidl

NameTypeDescriptionDefault
id uint16 No default
offset uint16 No default

HostBridgeInfo

Defined in fuchsia.hardware.pci/pci.fidl

NameTypeDescriptionDefault
start_bus_number uint8 No default
end_bus_number uint8 No default
segment_group uint16 No default

CONSTANTS

NameValueTypeDescription
BASE_ADDRESS_COUNT 6 uint32
BASE_CONFIG_SIZE 256 uint32
MAX_CAPABILITIES 32 uint32
MAX_DEVICES 64 uint32
MAX_EXT_CAPABILITIES 32 uint32