fuchsia.hardware.amlogic.metadata

Performance domain ID.

A unique identifier that maps this performance domain to its operating points.

Number of logical processors in this performance domain.

An integer in the range [0-255] that defines the relative performance of this domain compared to others in the system.

A friendly name for this performance domain.

The index of the GPIO to use for each SPI device. GPIOs are expected to be fragments named "gpio-cs-n", where n is the valued stored in cs. Alternatively, entries may be set to CS_CLIENT_MANAGED to indicate that the client driver will manage the cs GPIO for this chip (or that cs isn't needed).

The clock divider register value (NOT the actual clock divider) to use for SCLK. If use_enhanced_clock_mode is true: - clock_divider_register_value is written to ENHANCE_CNTL, and must be in [0, 255]. - The bus clock frequency is: core clock / (2 * (clock_divider_register_value + 1)) If use_enhanced_clock_mode is false: - clock_divider_register_value is written to CONREG, and must be in [0, 7]. - The bus clock frequency is: core clock / (2 ^ (clock_divider_register_value + 2))

If true, the SPI driver uses the enhanced clock mode instead of the regular clock mode.

If true, the client is responsible for reversing the endianness of transfers when using DMA.

The value to use for the dlyctl field in TESTREG. The default value should work for low-speed peripherals.

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